magistraleinformaticanetworking:spm:istruzionixeonphi14
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| Entrambe le parti precedenti la revisioneRevisione precedenteProssima revisione | Revisione precedente | ||
| magistraleinformaticanetworking:spm:istruzionixeonphi14 [30/10/2014 alle 12:06 (10 anni fa)] – Marco Danelutto | magistraleinformaticanetworking:spm:istruzionixeonphi14 [11/11/2014 alle 09:41 (10 anni fa)] (versione attuale) – Marco Danelutto | ||
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| Please take into account that a minimal set of libraries is available on the mic. | Please take into account that a minimal set of libraries is available on the mic. | ||
| + | |||
| + | === FastFLow === | ||
| + | Please take into account that you need to inlcude the flag -DNO_DEFAULT_MAPPING when compiling FastFlow programs, as the default mapping at the moment assumes a core numbering such as the one used for Sandy/Ivy Bridge (0 first context of the first core, 1 first context of the second core ...) processors, which is different from the one used on PHI (0 first context of the first core, 1 second context of the first core ...). | ||
| + | |||
| + | === MIC0 and MIC1 === | ||
| + | You can use both the accelerators available on the machine (namely MIC0 and MIC1), despite the fact the examples in this page alway use mic0 ... | ||
| + | |||
| === Documentation === | === Documentation === | ||
| Available documentation on the Xeon PHI and the relative programming tools may be accessed at the [[https:// | Available documentation on the Xeon PHI and the relative programming tools may be accessed at the [[https:// | ||
magistraleinformaticanetworking/spm/istruzionixeonphi14.1414670790.txt.gz · Ultima modifica: 30/10/2014 alle 12:06 (10 anni fa) da Marco Danelutto